Memory controller, storage device and method for adjusting a data input/output speed of the controller based on internal and external temperature information

ABSTRACT

Provided herein may be a storage device and a method of operating the same. In a storage device for controlling operational performance depending on temperature, a memory controller configured to control a memory device may include an internal temperature sensing unit configured to generate an internal temperature information by sensing a temperature of the memory controller and a performance adjustment unit configured to receive an external temperature information from an external temperature sensing unit, and controlling operational performance of the memory controller using the internal temperature information and the external temperature information, wherein the external temperature information represents a temperature of the memory device.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is an application for reissue of U.S. Pat. No.10,282,271 issued May 7, 2019 on U.S. Non-Provisional patent applicationSer. No. 15/838,513 filed Dec. 12, 2017, and which claims priority under35 U.S.C. § 119(a) to Korean patent application number 10-2017-0067027filed on May 30, 2017, the entire disclosure of which is incorporatedherein by reference.

BACKGROUND Field of Invention

Various embodiments of the present disclosure generally relate to anelectronic device and, more particularly, to a storage device and amethod of operating the storage device.

Description of Related Art

A storage device is a device for storing data under the control of ahost device, such as a computer, a smart phone, or a smart pad. Examplesof the storage device include a device for storing data in a magneticdisk, as in the case of a hard disk drive (HDD), and a device forstoring data in a semiconductor memory, especially in a nonvolatilememory, as in the case of a solid state drive (SSD) or a memory card.

Representative examples of the nonvolatile memory include a read-onlymemory (ROM), a programmable ROM (PROM), an electrically programmableROM (EPROM) an electrically erasable and programmable ROM (EEPROM), aflash memory, a phase-change random access memory (PRAM), a magnetic RAM(MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc.

SUMMARY

Various embodiments of the present disclosure are directed to a storagedevice capable of adjusting the performance thereof depending ontemperature, and a method of operating the same.

An embodiment of the present disclosure may provide for a memorycontroller for controlling a memory device. The memory controller mayinclude an internal temperature sensing unit configured to generate aninternal temperature information by sensing a temperature of the memorycontroller and a performance adjustment unit configured to receive anexternal temperature information from an external temperature sensingunit, and controlling operational performance of the memory controllerusing the internal temperature information and the external temperatureinformation, wherein the external temperature information represents atemperature of the memory device.

An embodiment of the present disclosure may provide for a storagedevice. The storage device may include a plurality of memory devices, anexternal temperature sensing unit configured to generate an externaltemperature information by sensing a temperature of the respectivememory device and a memory controller configured to: control theplurality of memory devices, and control operational performance of thememory controller using internal temperature information and theexternal temperature information, wherein the internal temperatureinformation represents a temperature of the memory controller.

An embodiment of the present disclosure may provide for a method ofoperating a storage device, the storage device including a plurality ofmemory devices and a memory controller for controlling the memorydevices. The method may include, obtaining, when a write request for theplurality of memory devices is inputted, internal temperatureinformation representing a temperature of the memory controller;generating, when the storage device boots, a correction value based onthe internal temperature information and an external temperatureinformation representing a temperature of the respective memory devices;generating adjusted temperature information by applying the correctionvalue to the internal temperature information; and adjusting operationalperformance of the memory controller using the adjusted temperatureinformation and pre-stored critical temperature information.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a storage device according to anembodiment of the present disclosure.

FIG. 2 is a block diagram illustrating an exemplary configuration of aperformance adjustment unit shown in FIG. 1 .

FIG. 3 is a flowchart illustrating an exemplary operation of a memorycontroller shown in FIG. 1 .

FIG. 4 is a flowchart for illustrating an exemplary operation of thememory controller shown in FIG. 1 .

FIG. 5 is a flowchart for illustrating an exemplary operation of thememory controller shown in FIG. 1 .

FIG. 6 is a diagram illustrating an exemplary configuration of a memorydevice shown in FIG. 1 .

FIG. 7 is a diagram illustrating an exemplary embodiment of a memorycell array shown in FIG. 6 .

FIG. 8 is an exemplary circuit diagram illustrating one of memory blocksshown in FIG. 7 .

FIG. 9 is an exemplary circuit diagram illustrating one of the memoryblocks shown in FIG. 7 .

FIG. 10 is a diagram illustrating an exemplary configuration of thememory controller shown in FIG. 1 .

FIG. 11 is a block diagram illustrating a memory card system to whichthe storage device in accordance with an embodiment of the presentdisclosure is applied.

FIG. 12 is a block diagram illustrating an example of a solid statedrive (SSD) system to which the storage device in accordance with anembodiment of the present disclosure is applied.

FIG. 13 is a block diagram illustrating a user system to which thestorage device in accordance with an embodiment of the presentdisclosure is applied.

DETAILED DESCRIPTION

Example embodiments will now be described more fully hereinafter withreference to the accompanying drawings; however, they may be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the example embodiments to those skilled in the art.

In the drawing figures, dimensions may be exaggerated for clarity ofillustration. It will be understood that when an element is referred toas being “between” two elements, it can be the only element between thetwo elements, or one or more intervening elements may also be present.

Hereinafter, embodiments will be described with reference to theaccompanying drawings. Embodiments are described herein with referenceto cross-sectional illustrations that are schematic illustrations ofembodiments (and intermediate structures). As such, variations from theshapes of the illustrations as a result, for example, of manufacturingtechniques and/or tolerances, are to be expected. Thus, embodimentsshould not be construed as limited to the particular shapes of regionsillustrated herein but may include deviations in shapes that result, forexample, from manufacturing. In the drawings, lengths and sizes oflayers and regions may be exaggerated for clarity. Like referencenumerals in the drawings denote like elements.

Terms such as “first” and “second” may be used to describe variouscomponents, but they should not limit the various components. Thoseterms are only used for the purpose of differentiating a component fromother components. For example, a first component may be referred to as asecond component, and a second component may be referred to as a firstcomponent and so forth without departing from the spirit and scope ofthe present disclosure. Furthermore, “and/or” may include any one of ora combination of the components mentioned.

Furthermore, a singular form may include a plural from as long as it isnot specifically mentioned otherwise. Furthermore, “include/comprise” or“including/comprising” used in the specification represent that one orsnore components, steps operations, and elements may exist or be added.

Furthermore, unless defined otherwise all the terms used in thisspecification including technical and scientific terms have the samemeanings as would be generally understood by those skilled in therelated art. The terms defined in generally used dictionaries should beconstrued as having the same meanings as would be construed in thecontext of the related art, and unless clearly defined otherwise in thisspecification, should not be construed as having idealistic or overlyformal meanings.

It is also noted that in this specification, “connected/coupled” refersto one component not only directly coupling another component but alsoindirectly coupling another component through an intermediate component.On the other hand, “directly connected/directly coupled” refers to onecomponent directly coupling another component without an intermediatecomponent.

Hereinafter, embodiments of the present disclosure will be describedwith reference to the attached drawings to fully describe the presentdisclosure to a person having ordinary knowledge in the art to which thepresent disclosure pertains.

FIG. 1 is a diagram illustrating a storage device according to anembodiment of the present disclosure.

Referring to FIG. 1 , a storage device 50 may include a memory device100, a memory controller 200, and an external temperature sensing unit140.

The memory device 100 may store data. The memory device 100 is operatedunder the control of the memory controller 200. The memory device 100may include a memory cell array including a plurality of memory cells inwhich data is stored. Examples of suitable memory devices 100 include aDouble Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), aLow Power Double Data Rate4 (LPDDR4) SDRAM, a Graphics Double Data Rate(DDDR) SDRAM a Low Power DDR (LPDDR) SDRAM, a Rambus Dynamic RandomAccess Memory (RDRAM), a NAND flash memory, a vertical NAND flashmemory, a NOR flash memory device, a resistive random access memory(RRAM), a phase-change memory (PRAM), a magnetoresistive random accessmemory (MRAM) a ferroelectric random access memory (FRAM), or a spintransfer torque random access memory (STT-RAM). In an embodiment, thememory device 100 may be implemented as a three-dimensional (3D) arraystructure. The present disclosure may also be applied not only to aflash memory in which a charge storage layer is implemented as aconductive floating, gate (FG), but also to a charge trap flash (CTF)memory in which a charge storage layer is implemented as an insulatinglayer.

In operation, the memory device 100 may receive a command and an addressfrom the memory controller 200, and access a region, selected inresponse to the address, in the memory cell array. That is, the memorydevice 100 may perform an operation corresponding to the command on theregion selected in response to the address. For example, the memorydevice 100 may perform a program operation, a read operation, and anerase operation. During a program operation, the memory device 100 mayprogram data in the region selected in response to the address. During aread operation, the memory device 100 may read data from the regionselected in response to the address. During an erase operation, thememory device 100 may erase data stored in the region selected inresponse to the address.

The external temperature sensing unit 140 may sense the temperature ofthe memory device 100. In FIG. 1 , the external temperature sensing unit140 is provided as a separate unit from the memory device 100 and thememory controller 200 in the storage device 50 implemented as asemiconductor package. The location of the external temperature sensingunit 140 may be determined in consideration that the temperature of thememory device 100 is determined based on external temperatureinformation that is an output value of the external temperature sensingunit 140. In an embodiment, the external temperature sensing unit 140may be located adjacent to a component that is more or most sensitive totemperature-based control among the components of the memory device 100.For example, the external temperature sensing unit 140 may be arrangedeither on or adjacent to the surface of any one of the memory controller200 and the memory device 100.

In an embodiment, the external temperature sensing unit 140 may beincluded in the memory device 100 although not illustrated. In thiscase, the temperature sensing result by the external temperature sensingunit 140 may be provided through a communication interface between thememory controller 200 and the memory device 100.

The external temperature sensing unit 140 may include at least onesensor for detecting a temperature information. The external temperaturesensing unit 140 may include, for example a temperature sensor fordetecting temperature. In an embodiment, the external temperaturesensing unit 140 may include a plurality of temperature sensors locatedat different locations of the memory device.

Examples of suitable temperature sensors include a resistancetemperature detector (RTD) and a thermistor. However, other typetemperature sensors may also be used. The RTD may be a temperaturesensor that uses a metal material having high variation in resistancedepending on the temperature, for example, platinum (Pt), and detectsthe temperature by measuring the variation in the resistance of themetal material. The thermistor may be a semiconductor element obtainedby mixing and sintering oxides such as manganese, nickel, copper,cobalt, chrome, and iron oxides. A thermistor has the characteristicthat variation in its resistance is large for small temperature changes,hence, it can detect small temperature differences. A thermistor may bemanufactured and used in various forms. As an example of a thermistor,is a thermistor manufactured in the form of a chip in which electrodesare formed on both sides of the thermistor.

The memory controller 200 may control the operation of the memory device100 in response to a request from a host 300 or regardless of therequest from the host 300.

For example, the memory controller 200 may control the memory device 100so that a program operation, a read operation or an erase operation isperformed in response to a request received from the host 300. During aprogram operation, the memory controller 200 may provide a programcommand, an address, and data to the memory device 100. During a readoperation, the memory controller 200 may provide a read command and anaddress to the memory device 100. During an erase operation, the memorycontroller 200 may provide an erase command and an address to the memorydevice 100.

In an embodiment, the memory controller 200 may autonomously generate aprogram command, an address, and data without receiving a request fromthe host, and transmit them to the memory device 100. For example, thememory controller 200 may provide commands, addresses, and data to thememory device 100 to perform background operations, such as a programoperation for wear leveling and a program operation for garbagecollection.

The memory controller 200 may further include a performance adjustmentunit 210 and an internal temperature sensing unit 220.

The performance adjustment unit 210 may adjust the performance of thestorage device 50 depending on the temperature of the memory device 100.For example, the performance adjustment unit 210 may reduce theoperational performance of the storage device 50 in order to decreasethe temperature of the memory device 100 when the temperature of thememory device 100 exceeds a critical temperature. An operation forlimiting operational performance of the storage device 50 depending onthe temperature of the memory device 100 is referred to as a throttlingoperation.

In an embodiment, the throttling operation may be an operation ofcontrolling the data input/output speeds of the memory controller 200and the memory device 100. For example, when the temperature of thememory device 100 is higher than a critical temperature, the memorycontroller 200 may decrease the data input/output speed thereof. Thedata input/output speed may be adjusted by controlling the number ofdata input/output channels, the number of ways, or a time (e.g., tPROGor tREAD) required for a data write operation or a data read operation.Alternatively, the data input/output speed may be controlled bytemporarily holding the transmission of commands, addresses, and datafor performing a data write operation or a data read operation.Alternatively, the data input/output speed may be controlled bytransmitting commands, addresses, and data for performing a data writeoperation or a data read operation to the memory device 100 after adelay corresponding to a predetermined time has passed.

In an embodiment, the memory controller 200 may control a plurality ofmemory devices 100. In this case, the throttling operation may be anoperation of controlling the number of memory devices 100 that aresimultaneously accessed by the memory controller 200. For example, thememory controller 200 may decrease the number of memory devices 100 thatare simultaneously accessed if the temperature of each memory device 100is higher than a critical temperature.

In an embodiment, the throttling operation may be an operation oflowering the frequency of a timing signal or a clock signal that isinputted to the memory device 100 below a basic frequency. For example,the memory controller 200 may decrease the frequency of the timingsignal or the clock signal that is inputted to the memory device 100 tothe frequency lower than the basic frequency when the temperature of thememory device 100 is higher than the critical temperature.

In an embodiment, the throttling operation may be an operation ofactivating a cooler included in the storage device 50. For example thememory controller 200 may activate the cooler when the temperature ofthe memory device 100 is higher than the critical temperature.

In addition to the above-described throttling operations, any operationof allowing the memory controller 200 to limit operational performanceto decrease the temperature of the memory device 100 falls within thecategory of the throttling operation according to an embodiment of thepresent disclosure, and are not limited to the operations described inthe present specification.

The internal temperature sensing unit 220 may be included in the memorycontroller 200 to sense the internal temperature of the memorycontroller 200. Since the internal temperature sensing unit 220 isdisposed in the memory controller 200, the memory controller 200 mayeasily acquire internal temperature information through the internaltemperature sensing unit 220 by controlling an internal signal ratherthan a separate communication interface.

The internal temperature sensing unit 220 may include sensors fordetecting at least one piece of information in the same way as theexternal temperature sensing unit 140, and may include, for example, atemperature sensor for detecting temperature.

In an embodiment, the internal temperature sensing unit 220 mayperiodically sense the temperature of the memory controller 200 and maystore the sensed temperature information in the memory controller 200.

Since the internal temperature sensing unit 220 is included in thememory controller 200 and the external temperature sensing unit 140 isdisposed closer to the memory device 100, the memory controller 200 mayeasily and rapidly obtain the temperature information thereof from theinternal temperature sensing unit 220 while accurately obtaining thetemperature information of the memory device 100 from the externaltemperature sensing unit 140.

In accordance with an the present disclosure, the memory controller 200may limit the operational performance of the storage device 50 usingboth internal temperature information provided from the internaltemperature sensing unit 220 and external temperature informationprovided from the external temperature sensing unit 140.

A method by which the memory controller 200 performs the throttlingoperation according to an embodiment of the present disclosure will bedescribed in detail later with reference to FIGS. 2 to 5 .

The host interface 300 may communicate with the storage device 50 usingat least one of various communication methods such as Universal SerialBus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), HighSpeed Interchip (HSIC), Small Computer System Interface (SCSI),Peripheral Component Interconnection (PCI), PCI express (PCIe),Nonvolatile Memory express (NVMe), Universal Flash Storage (UFS), SecureDigital (SD), MultiMedia Card (MMC), embedded MMC (eMMC), Dual In-lineMemory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM(LRDIMM) communication methods.

FIG. 2 is a block diagram illustrating an exemplary configuration of theperformance adjustment unit 210 of FIG. 1 .

Referring to FIG. 2 , the performance adjustment unit 210 may include acorrection value generation unit 211, a performance adjustmentdetermination unit 212, and a correction value update control unit 213.

The correction value generation unit 211 may receive externaltemperature information Ex_T and internal temperature information In_T.The external temperature information Ex_T may indicate the temperaturesensing result by the external temperature sensing unit 140 as describedabove with reference to FIG. 1 . The internal temperature informationmay indicate the temperature sensing result by the internal temperaturesensing unit 220 as described above with reference to FIG. 1 . Thecorrection value generation unit 211 may generate a correction valuediff using, both the external temperature information Ex_T and theinternal temperature information In_T. For example, the correction valuegeneration unit 211 may generate a difference value between the externaltemperature information Ex_T and the internal temperature informationIn_T as the correction value diff. The correction value generation unit211 may output the generated correction value diff to the performanceadjustment determination unit 212.

In an embodiment, the correction value generation unit 211 may generatea correction value diff when external temperature information Ex_T andinternal temperature information In_T are simultaneously inputted.Alternatively, when external temperature information Ex_T is inputtedwhile internal temperature information In_T is continuously received,the correction value generation unit 211 may generate a correction valuediff in response to the inputted external temperature information Ex_T.Alternatively, the correction value generation unit 211 may generate acorrection value diff using both external temperature information Ex_Tand internal temperature information In_T in response to a controlsignal (not illustrated) that is inputted through a separate line.Alternatively, the correction value generation unit 211 may generate acorrection value diff in response to an update enable signal update_ENthat is inputted from the correction value update control unit 213,which will be described later.

The performance adjustment determination unit 212 may determine whetherto limit the operational performance of the storage device 50 dependingon the temperature. For example, the performance adjustmentdetermination unit 212 may output a throttling signal throttling_EN whenthe temperature of the memory device 100 is higher than a criticaltemperature.

The critical temperature may be a temperature at which the operationresult of the memory device is unreliable. In an embodiment, thecritical temperature may be a temperature that, cumulatively, affectsthe operating results of the memory device, even though it does not havean immediate effect on the memory device in itself. The criticaltemperature can be experimentally determined and stored in the memorycontroller.

In detail, the performance adjustment determination unit 212 may receivethe internal temperature information In_T and the correction value diff.The performance adjustment determination unit 212 may generate adjustedtemperature information in which the correction value diff is applied tothe internal temperature information In_T. The performance adjustmentdetermination unit 212 may compare the adjusted temperature informationwith pre-stored critical temperature information. When the adjustedtemperature information is higher than the critical temperatureinformation, the performance adjustment determination unit 212 mayoutput the throttling signal throttling_EN.

In an embodiment, the performance adjustment determination unit 212 maydetermine whether to limit the operational performance of the storagedevice 50 depending on the temperature as described above with referenceto FIG. 1 when a write request is inputted from a host 300. That is, theperformance adjustment determination unit 212 may generate adjustedtemperature information using both the internal temperature informationIn_T and the correction value diff when a write operation is performed,and may compare the adjusted temperature information with the criticaltemperature information.

The correction value update control unit 213 may output an update enablesignal update_EN to the correction value generation unit 211 when acondition activation signal cond_EN indicating that a condition forupdating the correction value diff has been satisfied is inputted. Whenthe update enable signal update_EN is inputted from the correction valueupdate control unit 213, the correction value generation unit 211 maygenerate a correction value diff using both the external temperatureinformation Ex_T and the internal temperature information In_T.

The condition enable signal cond_EN may be inputted if the condition forupdating the correction value is satisfied.

In an embodiment, the memory controller 200 may update the correctionvalue diff depending on the number of erase-write operations (i.e., thenumber of erase-write cycles: EW cycles) of the memory device 100. Forexample, the memory controller 200 may enable the condition activationsignal cond_EN that is an internal signal when the number of EW cyclesof the memory device 100 exceeds a threshold number.

In an embodiment, the memory controller 200 may update the correctionvalue diff whenever a preset reference time elapses. For example,whenever the preset reference time has elapsed, the memory controller200 may enable the condition activation signal cond_EN that is aninternal signal. In various embodiments, the preset reference time maybe set based on the Quality of Service (QoS) criteria of the memorydevice 100.

In an embodiment, when the value of the internal temperature informationIn_T is changed to exceed a critical value, the memory controller 200may update the correction value diff. For example, when the temperaturesensing result by the internal temperature sensing unit 220, which isdescribed above with reference to FIG. 1 is rapidly changed, that is,when the changed result is compared with a previously sensed result, andthe changed temperature sensing result exceeds a critical value, thememory controller 200 may enable the condition activation signal cond_ENthat is an internal signal.

FIG. 3 is a flowchart illustrating an exemplary operation of the memorycontroller 200. FIG. 3 illustrates an operation of the memory controller200 generating a correction value diff when the storage device boots upand storing the generated correction value diff.

Referring to FIG. 3 at step 301, power is supplied to the storage device50. When the power is supplied to the storage device 50, the memorycontroller 200 may perform a boot operation. The memory controller 200may perform operations, which ill be described at steps 303 to 307, asthe boot operation.

At step 303, the memory controller 200 may obtain the externaltemperature information that is the temperature sensing result by theexternal temperature sensing unit 140. In an embodiment, the temperaturesensing result by the external temperature sensing unit 140 may beprovided through a communication interface between the memory controller200 and the memory device 100. For example, the memory controller 200may obtain the external temperature information from the memory device100 using a get parameter command.

At step 305, the memory controller 200 may obtain the internaltemperature information from the internal temperature sensing unit 220.The internal temperature sensing unit 220 may be included in the memorycontroller 200. Therefore, the memory controller 200 may obtain theinternal temperature information that is the temperature sensing resultby the internal temperature sensing unit 220 in response to an internalcontrol signal.

At step 307, the memory controller 200 may generate a correction valuediff using a difference value between the external temperatureinformation and the internal temperature information. The memorycontroller 200 may store the generated correction value diff.

FIG. 4 is a flowchart illustrating an exemplary operation of the memorycontroller 200.

Referring, to FIG. 4 , at step 401, the memory controller 200 mayreceive a write request from an external host 300. The memory controller200 may determine whether to limit the operational performance of thestorage device 50 depending on the temperature, in response to the writerequest received from the external host 300.

At step 403, the memory controller 200 may obtain the internaltemperature information that is the temperature sensing result by theinternal temperature sensing unit 220. Since the internal temperaturesensing unit 220 is disposed in the memory controller 200, the memorycontroller 200 may obtain the internal temperature information inresponse to an internal control signal.

At step 405, the memory controller 200 may generate adjusted temperatureinformation in which the correction value diff is applied to theinternal temperature information. In detail, the correction value diffmay be a value that is previously stored based on the operationdescribed above with reference to FIG. 3 . That is, the correction valuediff may be a difference value between the external temperatureinformation that is the temperature sensing result by the externaltemperature sensing unit 140 and the internal temperature informationthat is the temperature sensing result by the internal temperaturesensing unit 220 when the storage device 50 boots. The memory controller200 may generate the adjusted temperature information in which thecorrection value diff is applied to the internal temperatureinformation, and may use the adjusted temperature information astemperature information of the memory device 100.

At step 407, the memory controller 200 may compare the adjustedtemperature information with critical temperature information. Thecritical temperature information may indicate a temperature at which thememory controller 200 starts to control the performance of the storagedevice 50. For example, the memory controller 200 may control theperformance of the storage device 50 when the temperature of the memorydevice 100 is higher than the critical temperature. If, as a result ofthe comparison at step 407, the adjusted temperature information ishigher than the critical temperature information, the process proceedsto step 409, whereas if, as a result of the comparison at step 407, theadjusted temperature information is lower than or equal to the criticaltemperature information, the process proceeds to step 411.

At step 409, the memory controller 200 may adjust the performance levelof the storage device 50. The memory controller 200 may control theperformance of the storage device 50 by increasing or decreasing theperformance level of the storage device 50. In detail, when the adjustedtemperature information is higher than the critical temperatureinformation, the temperature of the memory device 100 may be consideredto be higher than the critical temperature, and the operationperformance of the storage device 50 may be limited so as to decreasethe temperature of the memory device 100. As described above anoperation for limiting the performance of the storage device 50 isreferred to as the throttling operation.

In an embodiment, when the temperature of the memory device 100 ishigher than the critical temperature, the memory controller 200 mayreduce data input/output speed.

In an embodiment, when the temperature of the memory device 100 ishigher than the critical temperature, the memory controller 200 maydecrease the number of memory devices 100 that are simultaneouslyaccessed by the memory controller 200.

In an embodiment, when the temperature of the memory device 100 ishigher than the critical temperature, the memory controller 200 maydecrease the frequency of a timing signal or a dock signal that isinputted to the memory device 100 to a frequency lower than a basicfrequency.

In an embodiment, when the temperature of the memory device 100 ishigher than the critical temperature, the memory controller 200 mayactivate a cooler included in the storage device 50.

In addition to the above-described throttling operations, any operationof allowing the memory controller 200 to limit operational performanceto decrease the temperature of the memory device 100 fails within thecategory of the throttling operation according to an embodiment of thepresent disclosure, and are not limited to the operations described inthe present specification.

At step 411, the memory controller 200 may perform a write operationdepending on the set performance level. In detail, when the adjustedtemperature information is higher than the critical temperatureinformation, the memory controller 200 may perform a write operationdepending on the performance level adjusted at step 409, whereas whenthe adjusted temperature information is lower than or equal to thecritical temperature information, the memory controller 200 may performa write operation without adjusting the performance level.

In accordance with an embodiment of the present disclosure, the memorycontroller 200 may obtain the external temperature information at theboot time and may generate a correction value diff that is thedifference value between the internal temperature information and theexternal temperature information. Thereafter, when a write operation isperformed in response to a write request, the memory controller 200 maycompare temperature information obtained by applying the correctionvalue diff to the internal temperature information with the criticaltemperature information. Thus, even if the external temperatureinformation is not obtained whenever a write operation is performed thememory controller 200 may perform a throttling operation correspondingto the temperature of the memory device 100.

FIG. 5 is a flowchart illustrating an exemplary operation of the memorycontroller 200. FIG. 5 illustrates the memory controller 200 updating acorrection value diff generated at the boot time.

Referring to FIG. 5 , at step 501, the memory controller 200 may receivea write request from an external host 300. The memory controller 200 maydetermine whether to limit the performance of the storage device 50depending on the temperature, in response to the write request receivedfrom the external host 300.

At step 503, the memory controller 200 may obtain the internaltemperature information that is the temperature sensing result by theinternal temperature sensing unit 220. Since the internal temperaturesensing unit 220 is disposed in the memory controller 200, the memorycontroller 200 may obtain the internal temperature information inresponse to an internal control signal.

At step 505, the memory controller 200 may generate adjusted temperatureinformation in which the correction value diff is applied to theinternal temperature information. In detail, the correction value diffmay be a value that is previously stored based on the operationdescribed above with reference to FIG. That is, the correction valuediff may be a difference value between the external temperatureinformation that is the temperature sensing result by the externaltemperature sensing unit 140 and the internal temperature informationthat is the temperature sensing result by the internal temperaturesensing unit 220 when the storage device 50 boots. The memory controller200 may generate the adjusted temperature information in which thecorrection value diff is applied to the internal temperatureinformation, and may use the adjusted temperature information astemperature information of the memory device 100.

At step 507, the memory controller 200 may compare the adjustedtemperature information with critical temperature information. Thecritical temperature information may indicate a temperature at which thememory controller 200 starts to control the performance of the storagedevice 50. For example, the memory controller 200 may control theperformance of the storage device 50 when the temperature of the memorydevice 100 is higher than the critical temperature. If, as a result ofthe comparison at step 507, the adjusted temperature information ishigher than the critical temperature information, the process proceedsto step 509, whereas if, as a result of the comparison at step 507, theadjusted temperature information is lower than or equal to the criticaltemperature information, the process proceeds to step 515.

At step 509, the memory controller 200 may determine whether acorrection value update condition is satisfied. The correction valuediff may be generated depending on the embodiment as described abovewith reference to FIG. 3 at the boot time, but the difference valuebetween the external temperature information that is the temperaturesensing result by the external temperature sensing unit 140 and theinternal temperature information that is the temperature sensing resultby the internal temperature sensing unit 220 may change with the passageof time. Therefore, in order to perform a precise throttling operationdepending on the temperature, there is a need to update the correctionvalue diff. However, when the correction value diff is generatedwhenever a write operation is performed, the performance of the storagedevice 50 may be deteriorated, and thus the memory controller 200 mayupdate the correction value diff only when the correction value updatecondition is satisfied.

In an embodiment, the memory controller 200 may update the correctionvalue diff based on the number of erase-write cycles (EW cycles) of thememory device 100. For example, the memory controller 200 may determinethat the correction value update condition is satisfied when the numberof EW cycles exceeds a threshold number.

In an embodiment, the memory controller 200 may update the correctionvalue diff whenever a preset reference time has elapsed. For example,whenever the preset reference time has elapsed, the memory controller200 may determine that the correction value update condition issatisfied. In various embodiments, the preset reference time may be setbased on the Quality of Service (QoS) criteria of the memory device.

In an embodiment, when the value of the internal temperature informationis changed to exceed a critical value, the memory controller 200 mayupdate the correction value diff. For example, when the temperaturesensing result by the internal temperature sensing unit 220, which isdescribed above with reference to FIG. 1 , is rapidly changed, that is,when the changed result is compared with a previously sensed result, andthe changed temperature sensing result is changed to exceed the criticalvalue, the memory controller may determine that the correction valueupdate condition is satisfied.

As a result of the determination at step 509, if the correction valueupdate condition is satisfied, the process proceeds to step 511, whereasif the correction value update condition is not satisfied, the processproceeds to step 513.

At step 511, the memory controller 200 may update the correction valuediff In detail, the memory controller 200 may update the correctionvalue diff based on steps 303 to 307 as described above with referenceto FIG. 3 . After the correction value diff has been updated, the memorycontroller 200 may return to step 505 where adjusted temperatureinformation may be generated using the updated correction value diff.

At step 13, the memory controller 200 may adjust the performance levelof the storage device 50. The memory controller 200 may control theperformance of the storage device 50 by increasing or decreasing theperformance level of the storage device 50. In detail, when the adjustedtemperature information is higher than the critical temperatureinformation, the temperature of the memory device 100 may be consideredto be higher than the critical temperature, and the operationperformance of the storage device 50 may be limited so as to decreasethe temperature of the memory device 100. As described above, anoperation for limiting the performance of the storage device 50 isreferred to as the throttling operation.

In an embodiment, when the temperature of the memory device 100 ishigher than the critical temperature, the memory controller 200 mayreduce data input/output speed.

In an embodiment, when the temperature of the memory device 100 ishigher than the critical temperature, the memory controller 200 maydecrease the number of memory devices 100 that are simultaneouslyaccessed by the memory controller 200.

In an embodiment, when the temperature of the memory device 100 ishigher than the critical temperature, the memory controller 200 maydecrease the frequency of a timing signal or a clock signal that isinputted to the memory device 100 to a frequency lower than a basicfrequency.

In an embodiment, when the temperature of the memory device 100 ishigher than the critical temperature, the memory controller 200 mayactivate a cooler included in the storage device 50.

In addition to the above-described throttling operations, any operationof allowing the memory controller 200 to limit operational performanceto decrease the temperature of the memory device 100 falls within thecategory of the throttling operation according to an embodiment of thepresent disclosure, and are not limited to the operations described inthe present specification.

At step 515, the memory controller 200 may perform a write operationdepending on the set performance level. In detail, when the adjustedtemperature information is higher than the critical temperatureinformation and the correction value update condition is not satisfied,the memory controller 200 may perform a write operation depending on theperformance level adjusted at step 513, whereas when the adjustedtemperature information is lower than or equal to the criticaltemperature information, the memory controller 200 may perform a writeoperation without adjusting the performance level.

FIG. 6 is a diagram illustrating an exemplary configuration of thememory device 100 of FIG. 1 .

Referring to FIG. 6 , the memory device 100 may include a memory cellarray 110, a peripheral circuit 120, and a control logic 130.

The memory cell array 110 includes a plurality of memory blocks BLK1 toBLKz. The plurality of memory blocks BLK1 to BLKz are coupled to anaddress decoder 121 through row lines RL. The memory blocks BLK1 to BLKzare coupled to a read and write circuit 123 through bit lines BL1 toBLm. Each of the memory blocks BLK1 to BLKz includes a plurality ofmemory cells. In an embodiment, the plurality of memory cells arenonvolatile memory cells. In the plurality of memory cells, memory cellscoupled to the same word line are defined as a single page. That is, thememory cell array 110 is composed of a plurality of pages. In anembodiment, each of the plurality of memory blocks BLK1 to BLKz includedin the memory cell array 110 may include a plurality of dummy cells. Asthe dummy cells, one or more dummy cells may be coupled in seriesbetween a drain select transistor and the memory cells and between asource select transistor and the memory cells.

The memory cells of the memory device 100 may each be implemented as asingle-level cell (SLC) capable of storing a single data bit or amulti-level cell (MLC) capable of storing two or more data bits,including, for example, a triple-level cell (TLC) capable of storingthree data bits, or a quad-level cell (QLC) capable of storing four databits.

The peripheral circuit 120 may include an address decoder 121, a voltagegenerator 122, the read and write circuit 123, a data input/outputcircuit 124, and an external temperature sensing unit 125.

The peripheral circuit 120 may drive the memory cell array 110. Forexample, the peripheral circuit 120 may drive the memory cell array 110so that a program operation, a read operation, and an erase operationare performed.

The address decoder 121 is coupled to the memory cell array 110 throughrow lines L. The row lines RL may include drain select lines, wordlines, source select lines, and a common source line. In an embodiment,the word lines may include normal word lines and dummy word lines. In anembodiment, the row lines RL may further include a pipe select line.

The address decoder 121 is configured to be operated under the controlof the control logic 130. The address decoder 121 receives the addressADDR from the control logic 130.

The address decoder 121 is configured to decode a block address of thereceived address ADDR. The address decoder 121 selects at least onememory block from among the memory blocks BLK1 to BLKz in response tothe decoded block address. The address decoder 121 is configured todecode a row address of the received address ADDR. The address decoder121 may select at least one word line of the selected memory block byapplying voltages supplied from the voltage generator 122 to at leastone word line WL in response to the decoded row address.

During a program operation, the address decoder 121 may apply a programvoltage to the selected word line and apply a pass voltage having alevel lower than that of the program voltage to unselected word lines.During a program verify operation, the address decoder 121 may apply averify voltage to a selected word line and apply a verification passvoltage higher than the verify voltage to unselected word lines.

During a read operation, the address decoder 121 may apply a readvoltage to a selected word line and apply a pass voltage higher than theread voltage to unselected word lines.

In an embodiment, the erase operation of the memory device 10 may beperformed on a memory block basis. During an erase operation, theaddress ADDR input to the memory device 100 includes a block address.The address decoder 121 may decode the block address and select a singlememory block in response to the decoded block address. During the eraseoperation, the address decoder 121 may apply a ground voltage to wordlines coupled to the selected memory block.

In an embodiment, the address decoder 121 may be configured to decode acolumn address of the received address ADDR. A decoded column addressDCA may be transferred to the read and write circuit 123. In anexemplary embodiment, the address decoder 121 may include componentssuch as a row decoder, a column decoder, and an address buffer.

The voltage generator 122 is configured to generate a plurality ofvoltages using, an external supply voltage provided to the memory device1000. The voltage generator 122 is operated under the control of thecontrol logic 130.

In an embodiment, the voltage generator 122 may generate an internalsupply voltage by regulating the external supply voltage. Phe internalsupply voltage generated by the voltage generator 122 is used as anoperating voltage of the memory device 100.

In an embodiment, the voltage generator 122 may generate a plurality ofvoltages using an external supply voltage or an internal supply voltage.The voltage generator 122 may be configured to generate various voltagesrequired by the memory device 100. For example, the voltage generator122 may generate a plurality of program voltages, a plurality of passvoltages, a plurality of select read voltages, and a plurality ofunselect read voltages.

For example, the voltage generator 122 may include a plurality ofpumping capacitors for receiving the internal supply voltage and maygenerate a plurality of voltages by selectively activating the pumpingcapacitors under the control of the control logic 130.

The generated voltages may be supplied to the memory cell array 110 bythe address decoder 121.

The read and write circuit 123 includes first to m-th page buffers PB1to PBm. The first to m-th page buffers PB1 to PBm are coupled to thememory cell array 110 through the first to m-th bit lines BL1 to BLm,respectively. The first to m-th page buffers PB1 to PBm are operatedunder the control of the control logic 130.

The first to m-th page buffers PB1 to PBm perform data communicationwith the data input/output circuit 124. During a program operation, thefirst to m-th page buffers PB1 to PBm receive data to be stored DATAthrough the data input/output circuit 124 and data lines DL.

During a program operation, the first to m-th page buffers PB1 to PBmmay transfer the data DATA, received through the data input/outputcircuit 124, to selected memory cells through the bit lines BL1 to BLmwhen a program pulse is applied to each selected word line. The memorycells in the selected page are programmed based on the transferred dataDATA. Memory cells coupled to a bit line to which a program permissionvoltage (e.g. a ground voltage) is applied may have increased thresholdvoltages. Threshold voltages of memory cells coupled to a bit line towhich a program prohibition voltage (e.g. a supply voltage) is appliedmay be maintained. During a program verify operation, the first to m-thpage buffers read page data from the selected memory cells through thebit lines BL1 to BLm.

During a read operation, the read and write circuit 123 reads data DATAfrom the memory cells in the selected page through the bit lines BL, andoutputs the read data DATA to the data input/output circuit 124.

During an erase operation, the read and write circuit 123 may allow thebit lines BL to float. In an embodiment, the read and write circuit 123may include a column select circuit.

The data input/output circuit 124 is coupled to the first to m-th pagebuffers PB1 to PBm through the data lines DL. The data input/outputcircuit 124 is operated under the control of the control logic 130.

The data input/output circuit 124 may include a plurality ofinput/output buffers (not illustrated) for receiving input data. Duringa program operation, the data input/output circuit 124 receives data tobe stored DATA from an external controller (not shown). During a readoperation, the data input/output circuit 124 outputs the data, receivedfrom the first to m-th page buffers PB1 to PBm included in the read andwrite circuit 123, to the external controller.

The external temperature sensing unit 123 may be the externaltemperature sensing unit 140 as described above with reference to FIGS.1 to 5 . The external temperature sensing unit 125 may sense thetemperature of the memory device 100 and provide the sensing result tothe control logic 130. The external temperature sensing unit 125 mayinclude at least one sensor for detecting at least one piece ofinformation, and may include, for example, a temperature sensor fordetecting temperature. The types of temperature sensors included in theexternal temperature sensing unit 125 are not limited by embodiments ofthe present disclosure. For example, examples of the temperature sensorsmay include a resistance temperature detector (RTD), a thermistor, etc.The RTD may be a temperature sensor that uses a metal material havinghigh variation in resistance depending on the temperature, for example,platinum (Pt), and detects the temperature by measuring the variation inthe resistance of the metal material. The thermistor is a semiconductorelement obtained by mixing and sintering oxides such as manganese,nickel, copper, cobalt, chrome, and iron oxides, and has acharacteristic that variation in resistance is large for a smalltemperature change. Such a thermistor may be manufactured and used invarious forms. For example, the thermistor may be manufactured in theform of a chip in which electrodes are formed on both sides.

The control logic 130 may be coupled t the address decoder 121, thevoltage generator 122, the read and write circuit 123, the datainput/output circuit 124, and the external temperature sensing unit 125.The control logic 130 may control the overall operation of the memorydevice 100. The control logic 130 may be operated in response to acommand CMD received from an external device. In an embodiment, thecontrol logic 130 may provide external temperature information that isthe temperature sensing result by the external temperature sensing unit125 to an external controller in response to the command from theexternal controller.

FIG. 7 is a diagram illustrating an embodiment of the memory cell arrayof FIG. 6 .

Referring to FIG. 7 , the memory cell array 110 includes a plurality ofmemory blocks BLK1 to BLKz. Each memory block has a three-dimensional(3D) structure. Each memory block includes a plurality of memory cellsstacked on a substrate. Such memory cells are arranged along a positiveX (+X) direction, a positive Y (+Y) direction, and a positive Z (+Z)direction. An exemplary configuration of each memory block will bedescribed in detail below with reference to FIGS. 8 and 9 .

FIG. 8 is an exemplary circuit diagram illustrating any one (BLK1) ofthe memory blocks BLK1 to BLKz of FIG. 7 .

Referring to FIG. 8 , the first memory block BLK1 includes a pluralityof cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment each ofthe cell strings CS11 to CS1m and CS21 to CS2m may be formed in a ‘U’shape. In the first memory block BLK1, m cell strings are arranged in arow direction (i.e. a positive (+) X direction). In FIG. 8 , two cellstrings are shown as being arranged in a column direction (i.e. apositive (+) y direction). However, this illustration is made forconvenience of description and it will be understood that three or morecell strings may be arranged in the column direction.

Each of the plurality of cell strings CS11 to CS1m and CS21 to CS2mincludes at least one source select transistor SST, first to n-th memorycells MC1 to MCn, a pipe transistor PT, and at least one drain selecttransistor DST.

The select transistors SST and DST and the memory cells MC1 to MCn mayhave similar structures, respectively. In an embodiment, each of theselect transistors SST and DST and the memory cells MC1 to MCn mayinclude a channel layer, a tunneling insulating layer, a charge storagelayer, and a blocking insulating layer. In an embodiment, a pillar forproviding the channel layer may be provided to each cell string. In anembodiment, a pillar for providing at least one of the channel layer,the tunneling insulating layer, the charge storage layer, and theblocking insulating layer may be provided to each cell string.

The source select transistor SST of each cell string is connectedbetween the common source line CSL and memory cells MC1 to MCp.

In an embodiment, the source select transistors of cell strings arrangedin the same row are coupled to a source select line extended in a rowdirection, and source select transistors of cell strings arranged indifferent rows are coupled to different source select lines. In FIG. 8source select transistors of cell strings CS11 to CS1m in a first roware coupled to a first source select line SSL1. The source selecttransistors of cell strings CS21 to CS2m in a second row are coupled toa second source select line SSL2.

In an embodiment, source select transistors of the cell strings CS11 toCS1m and CS21 to CS2m may be coupled in common to a single source selectline.

The first to n-th memory cells MC1 to MCn in each cell string arecoupled between the source select transistor SST and the drain selecttransistor DST.

The first to n-th memory cells MC1 to MCn may be divided into first top-th memory cells MC1 to MCp and p+1-th to n-th memory cells MCp+1 toMCn. The first to p-th memory cells MC1 to MCp are sequentially arrangedin a direction opposite a positive (+) Z direction and are connected inseries between the source select transistor SST and the pipe transistorPT. The p+1-th to n-th memory cells MCp+1 to MCn are sequentiallyarranged in the +Z direction and are connected in series between thepipe transistor P and the drain select transistor DST. The first to pathmemory cells MC1 to MCp and the p+1-th to n-th memory cells MCp+1 to MCnare coupled to each other through the pipe transistor PT. The gates ofthe first to n-th memory cells MC1 to MCn of each cell string arecoupled to first to n-th word lines WL1 to WLn, respectively.

The gate of the pipe transistor PT of each cell string is coupled to apipeline PL.

The drain select transistor DST of each cell string is connected betweenthe corresponding bit line and the memory cells MCp+1 to MCn. The cellstrings in a row direction are coupled to drain select lines extended ina row direction. Drain select transistors of cell strings CS11 to CS1min the first row are coupled to a first drain select line DSL1. Drainselect transistors of cell strings CS21 to CS2m in a second row arecoupled to a second drain select line DSL2.

Cell strings arranged in a column direction are coupled to bit linesextended in a column direction. In FIG. 8 , cell strings CS11 and CS21in a first column are coupled to a first bit line BL1. Cell strings CS1mand CS2m in an m-th column are coupled to an m-th bit, line BLm.

The memory cells coupled to the same word line in cell strings arrangedin a row direction constitute a single page. For example, memory cellscoupled to the first word line WL1, among the cell strings CS11 to CS1min the first row, constitute a single page. Memory cells coupled to thefirst word line WL1, among the cell strings CS21 to CS2m in the secondrow, constitute a single additional page. Cell strings arranged in thedirection of a single row may be selected by selecting any one of thedrain select lines DSL1 and DSL2. A single page may be selected from theselected cell strings by selecting any one of the word lines WL1 to WLn.

In an embodiment, even bit lines and odd bit lines, instead of first tom-th bit lines BL1 to BLm, may be provided. Further, even-numbered cellstrings, among the cell strings CS11 to CS1m or CS21 to CS2m arranged ina row direction, may be coupled to the even bit lines, respectively, andodd-numbered cell strings, among the cell strings CS11 to CS1m or CS21to CS2m arranged in the row direction, may be coupled to the odd bitlines, respectively.

In an embodiment, one or more of the first to n-th memory cells MC1 toMCn may be used as dummy memory cells. For example, one or more dummymemory cells are provided to reduce an electric field between the sourceselect transistor SST and the memory cells MC1 to MCp. Alternatively,the one or more dummy memory cells are provided to reduce an electricfield between the drain select transistor DST and the memory cells MCp+1to MCn. As more dummy memory cells are provided, the reliability of theoperation of the memory block BLK1 is improved, but the size of thememory block BLK1 is increased. As fewer memory cells are provided, thesize of the memory block BLK1 is reduced, but the reliability of theoperation of the memory block. BLK1 may be deteriorated.

In order to efficiently control the one or more dummy memory cells, eachof the dummy memory cells may have a required threshold voltage. Beforeor after the erase operation of the memory block BLK1 is performed, aprogram operation may be performed on all or some of the dummy memorycells. When an erase operation is performed after the program operationhas been performed, the threshold voltages of the dummy memory cellscontrol the voltages that are applied to the dummy word lines coupled torespective dummy memory cells, and thus the dummy memory cells may haverequired threshold voltages.

FIG. 9 is an exemplary circuit diagram illustrating an embodiment BLK1′of any one (BLK1) of the memory blocks BLK1 to BLKz of FIG. 7 .

Referring to FIG. 9 , a first memory block BLK1 includes a plurality ofcell strings CS11′ to CS1m′ and CS21′ to CS2m′. Each of the plurality ofcell strings CS11′ to CS1m′ and CS21 to CS2m′ is extended along apositive Z (+Z) direction. Each of the cell strings CS11′ to CS1m′ andCS21′ to CS2m′ includes at least one source select transistor SST, firstto n-th memory cells MC1 to MCn, and at least one drain selecttransistor DST, which are stacked on a substrate (not illustrated) belowthe memory block BLK1′.

The source select transistor SST of each cell string connected between acommon source line CSL and memory cells MC1 to MCn. The source selecttransistors of cell strings arranged in the same row are coupled to thesame source select line. Source select transistors of cell strings CS11′to CS1m′ arranged in a first row are coupled to a first source selectline SSL1. Source select transistors of cell strings CS21′ to CS2m′arranged in a second row are coupled to a second source select lineSSL2. In an embodiment, source select transistors of the cell stringsCS11′ to CS1m′ and CS21 to CS2m′ may be coupled in common to a singlesource select line.

The first to n-th memory cells MC1 to MCn in each cell string areconnected in series between the source select transistor SST and thedrain select transistor DST. The gates of the first to n-th memory cellsMC1 to MCn are coupled to first to n-th word lines WL1 to WLn,respectively.

The drain select transistor DST of each cell string is connected betweenthe corresponding bit line and the memory cells MC1 to MCn. Drain selecttransistors of cell strings arranged in a row direction are coupled todrain select lines extended in a row direction. The drain selecttransistors of the cell strings CS11′ to CS1m′ in the first row arecoupled to a first drain select line DSL1. The drain select transistorsof the cell strings CS21′ to CS2m′ in the second row are coupled to asecond drain select line DSL2.

As a result, the memory block BLK1′ of FIG. 9 has an equivalent circuitsimilar to that of the memory block BLK1 of FIG. 8 except that a pipetransistor PT is excluded from each cell string.

In an embodiment, even bit lines and odd bit lines, instead of first tom-th bit lines BL1 to BLm may be provided. Further, even-numbered cellstrings, among the cell strings CS11″ to CS1m′ or CS21′ to CS2m′arranged in a row direction, may be coupled to the even bit lines,respectively, and odd-numbered cell strings, among the cell stringsCS11′ to CS1m′ or CS21′ to CS2m′ arranged in the row direction, may becoupled to the odd bit lines, respectively.

In an embodiment, one or more of the first to n-th memory cells MC1 toMCn may be used as dummy memory cells. For example, the one or moredummy memory cells are provided to reduce an electric field between thesource select transistor SST and the memory cells MC1 to MCn.Alternatively, the one or more dummy memory cells are provided to reducean electric field between the drain select transistor DST and the memorycells MC1 to MCn. As more dummy memory cells are provided, thereliability of the operation of the memory block BLK1′ is improved, butthe size of the memory block BLK1′ is increased. As fewer memory cellsare provided, the size of the memory block BLK1′ is reduced, but thereliability of the operation of the memory block BLK1′ may bedeteriorated.

In order to efficiently control the one or more dummy memory cells, eachof the dummy memory cells may have a required threshold voltage. Beforeor after the erase operation of the memory block BLK1′ is performed, aprogram operation may be performed on all or some of the dummy memorycells. When an erase operation is performed after the program operationhas been performed, the threshold voltages of the dummy memory cellscontrol the voltages that are applied to the dummy word lines coupled torespective dummy memory cells, and thus the dummy memory cells may haverequired threshold voltages.

FIG. 10 is a diagram illustrating an embodiment of the memory controllerof FIG. 1 .

A memory controller 1000 is coupled to a host and a memory device. Inresponse to a request from the host, the memory controller 1000 mayaccess the memory device. For example, the memory controller 1000 may beconfigured to control write, read, erase, and background operations ofthe memory device. The memory controller 1000 may provide an interfacebetween the memory device and the host. The memory controller 1000 mayrun firmware for controlling the memory device.

Referring to FIG. 10 , the memory controller 1000 may include aprocessor 1010, a memory buffer 1020, an error correction code (ECC)block 1030, a host interface 1040, a buffer control circuit 1050, amemory interface 1060, and a bus 1070. The memory controller may alsoinclude a performance adjustment unit 210 and an internal temperaturesensing unit 220 as in the embodiment of FIG. 1 . The memory controller2100 may be implemented in the same way as the memory controller 200,described above with reference to FIG. 1 .

The bus 1070 may provide channels between components of the memorycontroller 1000.

The processor 1010 may control the overall operation of the memorycontroller 1000 and may perform a logical operation. The processor 1010may communicate with an external host through the host interface 1040and also communicate with the memory device through the memory interface1060. Further, the processor 1010 may communicate with the memory buffer1020 through the buffer control circuit 1050. The processor 1010 maycontrol the operation of the storage device by using the memory buffer1020 as a working memory, a cache memory or a buffer memory.

The processor 1010 may perform the function of a flash translation layer(FTL). The processor 1010 may translate a logical block address (LBA),provided by the host into a physical block address (PBA) through theFTL. The FTL may receive the LBA using a mapping table and translate theLBA into the PBA. Examples of an address mapping method performedthrough the FTL may include various methods according to a mapping unit.Representative address mapping methods include a page mapping method, ablock mapping method, and a hybrid mapping method.

The processor 1010 may randomize data received from the host. Forexample, the processing unit 1010 may use a randomizing seed torandomize data received from the host. The randomized data may beprovided, as data to be stored, to the memory device and may beprogrammed in the memory cell array.

The processor may derandomize data received from the memory deviceduring a read operation. For example the processor 1010 may derandomizethe data received from the memory device using a derandomizing seed. Thederandomized data may be outputted to the host.

In an embodiment, the processor 1010 may run software or firmware toperform randomizing and derandomizing operations.

In an embodiment, the processor 1010 may perform the operation of theperformance adjustment unit 210, described above with reference to FIGS.1 and 2 . For example, the processor 1010 may run firmware for adjustingthe performance of the storage device depending on the temperature ofthe memory device. The firmware for adjusting the performance of thestorage device depending on the temperature may run based on theoperating method of the memory controller, described above withreference to FIGS. 2 to 5 .

The memory buffer 1020 may be used as a working memory, a cache memory,or a buffer memory of the processor 1010. The memory buffer 1020 maystore codes and commands executed by the processor 1010. The memorybuffer 1020 may store data that is processed by the processor 1010. Thememory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM(DRAM).

The ECC block 1030 may perform error correction. The ECC block 1030 mayperform ECC encoding based on data to be written to the memory devicethrough the memory interface 1060. The ECC-encoded data may betransferred to the memory device through the memory interface 1060. TheECC block 1030 may perform ECC decoding based on data received from thememory device through the memory interface 1060. In an example, the ECCblock 1030 may be included as the component of the memory interface 1060in the memory interface 1060.

The host interface 1040 may communicate with the external host under thecontrol of the processor 1010. The host interface 1040 may performcommunication using at least one of various communication methods suchas Universal Serial Bus (USB), Serial AT Attachment (SATA), SerialAttached SCSI (SAS), High Speed Interchip (HSIC), Small Computer SystemInterface (SCSI), Peripheral Component Interconnection (PCI), PCIexpress (PCIe), Nonvolatile Memory express (NVMe), Universal FlashStorage (UFS), Secure Digital (SD), MultiMedia Card (MMC), embedded MMC(eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), andLoad Reduced DIMM (LRDIMM) communication methods.

The buffer control circuit 1050 may control the memory buffer 1020 underthe control of the processor 1010.

The memory interface 1060 may communicate with the memory device underthe control of the processor 1010. The memory interface 1060 maytransmit/receive commands, addresses, and data to/from the memory devicethrough channels.

In an embodiment, the memory controller 1000 may not include the memorybuffer 1020 and the buffer control circuit 1050.

In an embodiment, the processor 1010 may control the operation of thememory controller 1000 using codes. The processor 1010 may load codesfrom a nonvolatile memory device (e.g. ROM) provided in the memorycontroller 1000. In an embodiment, the processor 1010 may load codesfrom the memory device through the memory interface 1060.

In an embodiment, the bus 1070 of the memory controller 1000 may bedivided into a control bus and a data bus. The data bus may beconfigured to transmit data in the memory controller 1000, and thecontrol bus may be configured to transmit control information such ascommands or addresses in the memory controller 1000. The data bus andthe control bus may be isolated from each other, and may neitherinterfere with each other nor influence each other. The data bus may becoupled to the host interface 1040, the buffer control circuit 1050, theECC block 1030, and the memory interface 1060. The control bus may becoupled to the host interface 1040, the processor 1010, the buffercontrol circuit 1050, the memory buffer 1020, and the memory interface1060.

FIG. 11 is a block diagram illustrating a memory card system, to whichthe storage device according to an embodiment of the present disclosureis applied.

Referring to FIG. 11 , a memory card system 2000 may include a memorycontroller 2100, a memory device 2200, and connector 2300.

The memory controller 2100 is coupled to the memory device 2200. Thememory controller 2100 may access the memory device 2200. For examplethe memory controller 2100 may be control read, write, erase, andbackground operations of the memory device 2200. The memory controller2100 may provide an interface between the memory device 2200 and a host.The memory controller 2100 may run firmware for controlling the memorydevice 2200. The memory controller 2100 may be implemented in the sameway as the memory controller 200, described above with reference to FIG.1 .

In an embodiment, the memory controller 2100 may include components,such as a RAM, a processing unit, a host interface, a memory interface,and an ECC block.

The memory controller 2100 may communicate with an external devicethrough the connector 2300. The memory controller 2100 may communicatewith an external device (e.g., a host) based on a specific communicationprotocol. In an embodiment, the memory controller 2100 may communicatewith the external device through at least one of various communicationprotocols such as universal serial bus (USB), multimedia card (MMC),embedded MMC (eMMC), peripheral component interconnection (PCI),PCI-express (PCI-E), advanced technology attachment (ATA), serial-ATA(SATA), parallel-ATA (PATA), small computer small interface (SCSI),enhanced small disk interface (ESDI), integrated drive electronics(IDE), Firewire, universal flash storage (UFS), WiFi, Bluetooth, andnonvolatile memory express (NVMe) protocols. In an embodiment, theconnector 2300 may be defined by at least one of the above-describedvarious communication protocols.

In an embodiment, the memory device 2200 may be implemented as any ofvarious nonvolatile memory devices, such as an Electrically Erasable andProgrammable ROM (EEPROM), a NAND flash memory, a NOR flash memory, aPhase-change RAM (PRAM), a Resistive RAM (ReRAM), a Ferroelectric RAM(FRAM), a Spin-Torque Magnetic RAM (STT-MRAM).

The operation of controlling the performance of the storage devicedepending on the temperature of the memory device, described above withreference to FIGS. 1 to 5 , may be performed by the memory controller2100. In this case, the external temperature sensing unit 140, describedabove with reference to FIG. 1 may be disposed in the memory device2200. Alternatively, although not illustrated in the drawing theexternal temperature sensing unit 140 may be implemented on the memorycard system 2000, independently of the memory controller 2100 and thememory device 2200.

In an embodiment, the memory controller 2100 or the memory device 2200may be packaged in a type such as Package on Package (PoP), Ball gridarrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier(PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die inWafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP),Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), SmallOutline (SOIC), Shrink Small Outline Package (SSOP). Thin Small Outline(TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-levelFabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), orthe like and may be provided as a single semiconductor package.Alternatively, the memory device 2200 may include a plurality ofnonvolatile memory chips, which may be packaged based on theabove-described package types and may be provided as a singlesemiconductor package.

In an embodiment, the memory controller 2100 and the memory device 2200may be integrated into a single semiconductor device. In an embodiment,the memory controller 2100 and the memory device 2200 may be integratedinto a single semiconductor device to configure a solid state drive(SSD). The memory controller 2100 and the memory device 2200 may beintegrated into a single semiconductor device to configure a memorycard. For example, the memory controller 2100 and the memory device 2200may be integrated into a single semiconductor device to configure amemory card such as a PC card (personal computer memory cardinternational association: PCMCIA), a compact flash card (CF), a smartmedia card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC,MMCmicro or eMMC), a SD card (SD, miniSD, microSD, or SDHC), or auniversal flash storage (UFS).

In an embodiment, the memory device 2200 may be the memory device 100,described above with reference to FIGS. 1 and 6 to 9 . That is, thememory device 2200 may, be operated based on the throttling operation,described above with reference to FIGS. 1 to 5 .

FIG. 12 is a block diagram illustrating an example of a solid statedrive (SSD) system to which the storage device according to anembodiment of the present disclosure is applied.

Referring FIG. 12 an SSD system 3000 may include a host 3100 and an SSD3200. Phe SSD 3200 may exchange signals SIG with the host 3100 through asignal connector 3001 and may receive power PWR through a powerconnector 3002. The SSD 3200 may include an SSD controller 3210, aplurality of flash memories 3221 to 322n, an auxiliary power supply3230, and a buffer memory 3240.

In an embodiment, the SSD controller 3210 may perform the function ofthe memory controller 200, described above with reference to FIG. 1 .

The SSD controller 3210 may control the plurality of flash memories 3221to 322n in response to the signals SIG received from the host 3100. Inan embodiment, the signals SIG may be signals based on the interfaces ofthe host 3100 and the SSD 3200. For example, the signals SIG may besignals defined by at least one of various interfaces such as universalserial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheralcomponent interconnection (PCI), PCI-express (PCI-E), advancedtechnology attachment (ATA), serial-ATA (SATA), parallel-ATA (PATA),small computer small interface (SCSI), enhanced small disk interface(ESDI), integrated drive electronics (IDE). Firewire, universal flashstorage (UFS), WiFi, Bluetooth, and nonvolatile memory express (NVMe)interfaces.

The auxiliary power supply 3230 may be coupled to the host 3100 throughthe power connector 3002. The auxiliary power supply 3230 may besupplied with power PWR from the host 3100 and may be charged. Theauxiliary power supply 3230 may supply the power of the SSD 3200 whenthe supply of power from the host 3100 is not smoothly performed. In anembodiment, the auxiliary power supply 3230 may be positioned inside theSSD 3200 or positioned outside the SSD 3200. For example, the auxiliarypower supply 3230 may be disposed in a main board and may supplyauxiliary power to the SSD 3200.

The buffer memory 3240 functions as a buffer memory of the SSD 3200. Forexample, the buffer memory 3240 may temporarily store data received fromthe host 3100 or data received from the plurality of flash memories 3221to 322n or may temporarily store met data (e.g., mapping tables) of theflash memories 3221 to 322n. The buffer memory 3240 may include volatilememories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM ornonvolatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

In an embodiment, the nonvolatile memories 3221 to 322n may be thenonvolatile memory devices, described above with reference to FIGS. 1 to11 . That is, the nonvolatile memories 3221 to 322n may erase memoryblocks based on the erase method, described above with reference toFIGS. 1 to 11 .

In an embodiment, the memory devices 3221 to 322n may be the memorydevice 100, described above with reference to FIGS. 1 and 6 to 9 . Thatis, the memory devices 3221 to 322n may be operated based on thethrottling operation, described above with reference to FIGS. 1 to 5 .

FIG. 13 is a block diagram illustrating a user system to which thestorage device according to an embodiment of the present disclosure isapplied.

Referring to FIG. 13 , a user system 4000 may include an applicationprocessor 3100, a memory module 4200, a network module 4300, a storagemodule 4400, and a user interface 4500.

The application processor 4100 may run components included in the usersystem 4000, an Operating System (OS) or a user program. In anembodiment the application processor 4100 may include controllers,interfaces, graphic engines, etc. for controlling the componentsincluded in the user system 4000. The application processor 4100 may beprovided as a system-on-chip (SoC).

The memory module 4200 may function as a main memory, a working memory,a buffer memory or a cache memory of the user system 4000. The memorymodule 4200 may include volatile RAMs such as DRAM, SDRAM, DDR SDRAM,DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM, and LPDDR3 SDRAM ornonvolatile RAMs such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment,the application processor 4100 and the memory module 4200 may bepackaged based on package-on-package (POP) and may then be provided as asingle semiconductor package.

The network module 4300 may communicate with external devices. Forexample, the network module 4300 may support wireless communication,such as Code Division Multiple Access (CDMA), Global System for Mobilecommunication (GSM), wideband CDMA (WCDMA), CDMA-2000, Time DivisionMultiple Access (TDMA), Long Term Evolution (LTE), Wimax, WLAN, UWB,Bluetooth, or WiFi communication. In an embodiment, the network module4300 may be included in the application processor 4100.

The storage module 4400 may store data. For example, the storage module4400 may store data received from the application processor 4100.Alternatively, the storage module 4400 may transmit the data stored inthe storage module 4400 to the application processor 4100. In anembodiment, the storage module 4400 may be implemented as a nonvolatilesemiconductor memory device such as a Phase-change RAM (PRAM), aMagnetic RAM (MRAM), a Resistive RAM (RRAM), a NAND flash memory, a NORflash memory, or a NAND flash memory having a three-dimensional (3D)structure. In an embodiment, the storage module 4400 may be provided asa removable storage medium (i.e., removable drive), such as a memorycard or an external drive of the user system 400.

In an embodiment, the storage module 4400 may include a plurality ofnonvolatile memory devices, which may each be the memory device 100,described above with reference to FIGS. 1 and 6 to 9 . That is, thenonvolatile memory device included in the storage module 4400 may beoperated based on the throttling operation, described above withreference to FIGS. 1 to 5 .

The user interface 4500 may include interfaces which input data orinstructions to the application processor 4100 or output data to anexternal device. In an embodiment, the user interface 4500 may includeuser input interfaces such as a keyboard, a keypad, a button, a touchpanel, a touch screen, a touch pad, a touch ball, a camera, amicrophone, a gyroscope sensor, a vibration sensor, and a piezoelectricdevice. The user interface 4500 may further include user outputinterfaces such as a Liquid Crystal Display (LCD), an Organic LightEmitting Diode (OLED) display device, an Active Matrix OLEO (AMOLED)display device, an LED, a speaker, and a motor.

In accordance with the present disclosure, there are provided a storagedevice that controls the performance thereof depending on thetemperature and a method of operating the storage device.

While the exemplary embodiments of the present disclosure have beendisclosed for illustrative purposes, those skilled in the art willappreciate that various modifications, additions and substitutions arepossible. Therefore, the scope of the present disclosure must be definedby the accompanying claims and equivalents thereof rather than by theabove-described embodiments.

Although the embodiments of the present disclosure have been disclosed,those skilled in the art will appreciate that various modificationsadditions and substitutions are possible, without departing from thescope and spirit of the present disclosure.

In the above-discussed embodiments, all steps may be selectivelyperformed or skipped. In addition, the steps in each embodiment may notalways performed in regular order. Furthermore, the embodimentsdisclosed in the present specification and the drawings aims to helpthose with ordinary knowledge in this art more clearly understand thepresent disclosure rather than aiming to limit the bounds of the presentdisclosure. In other words one of ordinary skill in the art to which thepresent disclosure belongs will be able to easily understand thatvarious modifications are possible based on the technical scope of thepresent disclosure.

Embodiments of the present disclosure have been described with referenceto the accompanying drawings, and specific terms or words used in thedescription should be construed in accordance with the spirit of thepresent disclosure without limiting the subject matter thereof. Itshould be understood that many variations and modifications of the basicinventive concept described herein will still fall within the spirit andscope of the present disclosure as defined in the accompanying claimsand equivalents thereof.

What is claimed is:
 1. A memory controller for controlling a memorydevice, the memory controller comprising: an internal temperature sensorconfigured to generate an internal temperature information by sensing atemperature of the memory controller; and a performance adjusterconfigured to receive an external temperature information from anexternal temperature sensing unit, and controlling operationalperformance a data input/output speed of the memory controller using thean internal temperature information and the external temperatureinformation, wherein the external temperature information represents atemperature of the memory device, and wherein the performance adjustercomprises: a correction value generator configured to generate acorrection value based on the internal and external temperatureinformation; a performance adjustment determination circuit configuredto generate an adjusted temperature information, in which the correctionvalue is applied to the internal temperature information, to compare theadjusted temperature information with pre-stored critical temperatureinformation and then to determine whether to adjust the operationalperformance data input/output speed of the memory controller based on aresult of the comparing comparison; and a correction value updatecontroller configured to generate an update enable signal for updatingthe correction value, and to output the update enable signal when anumber of erase-write cycles (EW cycles) of the memory device exceeds athreshold number.
 2. The memory controller according to claim 1, whereinthe correction value generator generates the correction value when poweris supplied to the memory controller.
 3. The memory controller accordingto claim 1, wherein the correction value is a difference value betweenthe internal temperature information and the external temperatureinformation.
 4. The memory controller according to claim 1, wherein theperformance adjustment determination circuit adjuster controls theoperational performance data input/output speed by outputting athrottling signal for activating a throttling operation that adjusts theoperational performance data input/output speed of the memory controllerwhen a write request for the memory device is inputted and the adjustedtemperature information is higher than the critical temperatureinformation.
 5. The memory controller according to claim 4, wherein thethrottling operation is an operation of decreasing a the datainput/output speed of the memory controller.
 6. The memory controlleraccording to claim 4, wherein: the memory controller is capable ofsimultaneously accessing a plurality of memory devices, and thethrottling operation is an operation of decreasing a number of memorydevices that the memory controller simultaneously accesses.
 7. Thememory controller according to claim 4, wherein the throttling operationis an operation of decreasing a frequency of a timing signal or a clocksignal that is inputted to the memory device.
 8. The memory controlleraccording to claim 4, wherein the throttling operation is an operationof activating performance adjuster activates a cooler disposed outsidethe memory controller while the throttling operation is activated. 9.The memory controller according to claim 1, wherein the correction valueupdate controller outputs the update enable signal when the internaltemperature information is changed changes to exceed a critical value.10. The memory controller according to claim 1, wherein the correctionvalue update controller outputs the update enable signal when a presetreference time has elapsed.
 11. The memory controller according to claim10, wherein the preset reference time is set based on Quality of Service(QoS) criteria of the memory device.
 12. A storage device comprising: aplurality of memory devices; and an external temperature sensorconfigured to generate an external temperature information by sensing atemperature of the respective memory device; and a memory controllerconfigured to: control the plurality of memory devices, and controloperational performance a data input/output speed of the memorycontroller using an internal temperature information and the externaltemperature information, wherein the internal temperature informationrepresents a temperature of the memory controller, wherein the memorycontroller is configured to generate a correction value representing adifference value between the internal temperature information and theexternal temperature information, togenerate an adjusted temperatureinformation in which the correction value is applied to the internaltemperature informationand, to updatingupdate the correction value whena number of erase-write cycles (EW cycles) of the memory device exceedsa threshold number, and determine whether to adjust the datainput/output speed of the memory controller based on the adjustedtemperature information.
 13. The storage device according to claim 12,wherein the memory controller is configured to generate generates thecorrection value representing a difference value between the internaltemperature information and the external temperature information whenthe storage device boots, and wherein generates the adjusted temperatureinformation is generated in which the correction value is applied to theinternal temperature information at a time at which a write request forthe plurality of memory devices is inputted.
 14. The storage deviceaccording to claim 13, wherein the memory controller is configured tocontrol operational performance the data input/output speed by comparingthe adjusted temperature information with a pre-stored criticaltemperature information.
 15. A method of operating a storage device, thestorage device including a plurality of memory devices and a memorycontroller for controlling the memory devices, the method comprising:obtaining, when a write request for the plurality of memory devices isinputted, internal temperature information representing a temperature ofthe memory controller; generating, when the storage device boots, acorrection value based on the internal temperature information and anexternal temperature information representing a temperature of therespective memory devices; generating an adjusted temperatureinformation by applying the correction value to the internal temperatureinformation; adjusting operational performance a data input/output speedof the memory controller using the adjusted temperature information anda pre-stored critical temperature information; and updating thecorrection value in response to an update enable signal which isgenerated when a number of erase-write cycles (EW cycles) of the memorydevice exceeds a threshold number.
 16. The method according to claim 15,wherein the operational performance data input/output speed is adjustedwhen the adjusted temperature information exceeds the criticaltemperature information.
 17. The method according to claim 15, furthercomprising generating an update enable signal when the internaltemperature information is changed changes to exceed a critical value.